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cpu-pipeline

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Name		Name	Last commit message	Last commit date
mips-assembler		mips-assembler
report		report
single-circle		single-circle
ALU.v		ALU.v
ARITH.v		ARITH.v
BCD7.v		BCD7.v
COMP.v		COMP.v
CPU_CLK.v		CPU_CLK.v
CPU_Pipeline.v		CPU_Pipeline.v
CPU_Pipeline_test.v		CPU_Pipeline_test.v
Control.v		Control.v
DataMem.v		DataMem.v
EX.v		EX.v
ID.v		ID.v
IF.v		IF.v
LICENSE		LICENSE
LOGIC.v		LOGIC.v
MEM.v		MEM.v
Peripheral.v		Peripheral.v
README.md		README.md
ROM.v		ROM.v
SHIFT.v		SHIFT.v
UART.v		UART.v
UART_.v		UART_.v
alu_tb.v		alu_tb.v
baud_rate_gen.v		baud_rate_gen.v
baud_rate_gen_test.v		baud_rate_gen_test.v
digitube_scan.v		digitube_scan.v
regfile.v		regfile.v
uart_receiver.v		uart_receiver.v
uart_sender.v		uart_sender.v

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cpu-pipeline

Homework for digital circuit summer course 2016.

I just finish the pipeline part in it (CPU_Pipeline.v, IF.v, ID.v, EX.v, MEM.v).

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